After some further testing and prototyping, I’ve updated the gyrator board PCB to provide additional protection to the lower FET device with:
- Protection Zener (D3) between drain and source (through-hole)
- Back to back protection Zeners (D1 and D2) between gate and source to ensure positive gate bias for higher currents on jFETs and use of enhancement MOSFET
Layout was carefully adapted to ensure track separation due to HV in place. Result is that the new gyrator board provides all protection needed on the lower device and simplifies the build process
Here is an example of a completed board tested:
