My previous design wasn’t good for two reasons:
- Input capacitance was too high due to Miller effect.
- Overall gain wasn’t enough: 55dB was marginal as 60dB would be ideal for an MC stage. Obviously this doesn’t apply to an MM cartridge where 40dB should be more than ok.
Input capacitance
Why is this a problem with a high-mu triode? The Miller capacitance of triodes tend to complicate matters in the phono stages. How much in our case? Let’s see. Looking at the datasheet, worst case the capacitances of the 6S17 K-V are Cgk=3pF and Cga=1.8pF. Assuming a mu of 190, the total input capacitance due to Miller is Ci=Cgk+(mu+1)*Cga = 345pF. This input capacitance clearly rules most of the MM cartridges which need about 250pF (including cable and stray capacitances). The option of running the 6S7K-V in common cathode amplifier mode isn’t a good choice.
We need to get the most of the gain on the first stage and ideally exit first stage with 1V to have a all-in-one RIAA equalisation, which is the case of the LCR network discussed.
Best choice then is to consider a cascode stage. The cascode has the following advantages and disadvantages:
- Advantages: maximum gain
- Disadvantages: poor PSRR and high output impedance, like a pentode.
The high output impedance means we need to couple with a follower to avoid increasing distortion. This is not a problem, as we need to drive the LCR network, so a follower is needed anyway. If we DC-couple the follower then is better as we avoid a capacitor in the signal path
A hybrid cascode or a folded cascode are good options. I have implemented a folded cascode or shunt cascode in my previous RIAA design with great success.
A hybrid cascode input stage
If we consider the hybrid cascode then:
- We can use a quiet FET at the lower device as it has lower noise figure compared to the triode. A low-noise bipolar would be better
- Parallelling FETs will allow as to increase the gain whilst halving the noise. Challenge is to match FETs, but that is not a real challenge as I have a tracer!
The 2SK369 is great choice but not easy to find these days, an available good choice albeit the SMD packaging is the BF862, which has the following characteristics:
- IDSS from 10 to 25mA
- Gm = 45mS
- Crss = 1.9pF
- VDS max =25V
As slightly noisier version would be the LSK170. A great option here as well if we want to avoid SMD components.
The noise of the BF862 is en= 0.8nV/√Hz so the noise over the bandwidth is Vn(nV)=0.9 *√(20kHz -20 Hz) = 127nV. With a source of 0.3mV then the SNR is 20 log (0.3mV/127nV) = 67.5dB. The RIAA equalisation provides 3.4 dB noise advantage so the actual SNR is 69dB. The real problem is the 1/f noise which makes the JFET not great for the MC phono stage. Better to use a quieter bipolar, but that is another story. For more details please Read Morgan Jones’ chapter on RIAA which is excellent.
The cascode gain is gm * RL. With RL = 15KΩ then the gain should be around 45mS *15KΩ= 675 or 56dB. The hotter we run the BF892, the better is.
Running the FET to about 12V means that the CCS should provide 0.2V Vgk difference to bias the 6S17K-V to about 14.5mA. Downside of this design which elevates U1 grid from 0V means noise introduced by the CCS. The PSRR of the cascode is not good as said earlier, so I wouldn’t really bother much about elevating the grid from ground given that the HT supply should be really quiet anyway 🙂
If we look at the noise amplification by the grid, this noise is amplified mu times or about 45dB in our case. However, the CCS attenuates the rail noise about 80dB so we are still in a good place.
C5 should help shunting the noise at the grid. But why bothering about the grid noise when the PSRR is the main draw back of this stage? The problem is the divider formed by RL and the Ra+rds(mu+1). If the rds is about 5KΩ (quick eye look at the data sheet curves) for the BF892 then PSRR is 968k/(15KΩ+968KΩ) or 98% of supply noise will go through the first stage. This is a clear demonstration of why the PSRR of the cascode is really bad!
What is the load seen by the FET? Assuming 6S16K-V ra about 13KΩ and Mu of 190 then
RL seen by the FET is RL+RA/(mu+1) = 141Ω. This should be good enough to keep the FET distortion low.
In summary, a cascode stage like the one above can provide a high gain (i.e. 54.1dB) and very low distortion (THD<0.005% below 1Vrms). The 1MΩ cleary is not a representative load of the follower stage input impedance so we should expect a slightly lower distortion. The Spice result is too optimistic in my view, but at least shows that this stage should behave really well in practice.
The input capacitance is the Cgs capacitance of the FET only thanks to not having Miller creating any issues here, which in this Spice simulation is about 8pF which is in line with the 8-10pF shown in the datasheet at Vgs at 0V.
If we add the cathode follower and DC-couple it to the first stage, we make the 6C45P-E to operate in linear region by biasing it at Vgs of -0.9V which reduces the grid current and minimises distortion. This can be achieved nicely here as we are DC-coupling the follower and we don’t need a negative supply for the follower tail (R2). This was an additional drawback from my previous design iteration which led to a follower with higher distortion. We had to add a resistor (R5) with a filtering cap (C2) to reduce the HT voltage to levels acceptable by U2. Unfortunately the cascode requires a higher HT, 350V in this case.
What we should be looking as an option here is to add a parallel BF862 to double the transconductance, halving the noise from the FET and changing the 6S17K-V for a 6J52p or similar high mu.
Why changing the 6SK17-V for a 6J52p/D3a? The only drawback of the 6SK17-V in this circuit is as mentioned before, that the heater is connected to the cathode. This will make mandatory to have a really quiet filament supply, something that can be achieved, not an impossible task.
Let’s analyse in more detail why we want to increase the transconductance here. The gain of the cascode is given by gm*RL. Increasing the RL helps in a way to increase PSRR but demands a higher HT. This is more costly and we want to avoid this. However, if we instead increase the transconductance we then can achieve the same result without increasing the HT supply and keeping the resistor at its current value.
A variation, the shunt cascode version
So if we want to maximise transconductance we need to run the FETs at their highest current possible. This will give maximum gm but at a cost: higher current. The BF862 can do 20V or less so if we run it closer to 19V we can get 16mA. A pair will need 32mA of bias current which will push the requirement for a higher HT with same RL. Let’s make it clear that the 6J52P can do 32mA and a compromise could be achieved if needed.
Alternatively we can try Rod Coleman’s “shunt” cascode topology as he named it. The additional current needed by the FETs is provided by R6 (instead of a CCS) which if we make it wire-wound it will be the quietest option here:
So with R6 of 20K we can add the current needed. Note that we waste more than 5W on that resistor as well as 4W in the RL resistor. With this topology we can achieve 60dB but we double the input capacitance to 16pF. Not a problem at all. However, distortion seems to increase up to 0.02% at maximum output. Very acceptable anyway.
We achieve 6dB of gain increase at a higher cost, not sure if this is worth the extra complexity and cost in the supply.
If you are looking for further performance you can implement a proper shunt cascode here with a PNP transistor as the top device instead. The shunt resistor could be run from a lower voltage rail as well.
What to do next then?
If we want +60dB of gain in the phono stage and we factor in the 20dB loss introduced by the RIAA stage, this leave us with a requirement of a +24dB gain for the second stage which is easier to achieve with a mu-follower which will also drive the output cables. I think I will then revert to the folded cascode with one FET and probably the 6SK17-V
More to come, hopefully soon…
I’d appreciate your comments or thoughts!
just follow your idea Ale
Yeah, so much to try and so little time available!
Ale
I think your third circuit isn’t a folded (or shunt) cascode as you are using a n-channel fet with a valve. Folded cascode circuits use dissimilar polarity devices, in your case it would have to be a p-channel j-fet with the 6J52P. Also the RL must go to ground and not B+. What you have is a series cascode circuit with R6 providing additional current to increase the transconductance of the lower device (BF862) without decreasing the headroom of the cascode output.
Regards
Anthony
Ale
Sorry, you do mention implementing a “proper folded cascode” in the future. Perhaps a little hasty on my part, should have read the post to the end. Still it is a series cascode.
Hi Anthony, yes. Thanks for pointing that out, that is why I said proper folded as I didn’t know how to name the shunt resistor to bottom FET 🙂
cheers
Ale