Introduction

This is the first instalment of a series of blog posts around CCS for valve circuits. Hope you enjoy it as much as I did with the experiments conducted as a result of my interest in CCS-driven circuits.

The depletion cascoded CCS

It’s been long time since I’ve done some circuit analysis and algebra, hopefully I’ve got this right. Seems to get to the expected result, so hey: I’ve done it ok.

The analysis of this circuit starts by using the T-model of the MOSFET. I’ve omitted the parasitic capacitances to simplify the analysis. I leave you the challenge to add them in though. If we look at the typical self-biased depletion FET CCS we can find the output impedance by doing the following formulae crunching:

In summary, the output impedance looking from the source side is:

Whereas the ro is also known as rds, gm is the transconductance and mu is the voltage gain of the FET. Rs is the programming resistor of the CCS. So the output impedance is set by mu times the Rset. A big value indeed can be achieved. For example using the famous DN2540, at about 30mA of drain current (Id) the gm is 240mA/V and rds is 14-15kΩ @Vds<1V. This yields to a μ of 3,600. Morgan Jones found that rds could be around 31kΩ when Vds=100V, however he also found that gm was around 148mA/V for 30mA.  If the CCS is not cascoded, then we should consider the higher rds value as VDS will be greater than 20-30V at least. For an Rs=39Ω, the output impedance is at least 140MΩ.

When we cascode a pair of self-biased depletion FETs we get the effect of the multiplying two FET gains and therefore we can approximate the output impedance to:

I leave the maths to one of you out there who is good at this!

Things are not rosy as they look as the DN2540 is far from being an ideal candidate for a cascoded FET CCS. As we will see later, there are two key factors that play against this topology:

1. The self-biased cascoded CCS puts all the voltage handling (VDS) on the top device and pushes the lower device to minimum VDS due to VGS bias of top device. This pushes the lower device to operate in a region where rds is lower and also COSS is high
2. At low VDS (e.g. 1V) the input capacitance (Ciss) climbs to nearly 200pF, the output capacitance (Coss) to 180pF. These leakage impedances are less than 90kΩ at 10kHz so we should expect a dramatic reduction in the HF response of the CCS unless the VDS is kept to 20V or more (see below datasheet extract).

Clever minds will already ask can we not force lower device to operate at larger VDS? Yes, and there are some arrangements for this which introduces complexity. In addition, we could look at other FET with smaller capacitances for the lower device, now that the HV constrain isn’t there as the top device takes all the heavy lifting.

I will get back to this latter, now let’s look at the DN2540 depletion FET a bit more closer.

Tracing a DN2540

Tracing a depletion FET like the DN2540 is not an easy task. The high transconductance of the FET presents a challenge to most of the tracers out there. Luckily the Locky’s ICT seems to be capable of tracing it despite is mainly oriented for bipolar curve tracing. Ferrite beads are mandatory on the gate to produce smooth curves.

I started the plot of the transfer curve for VDS of 10V:

At first glance, we can say that VGS(off) isn’t what is published.In this case the VGS(off) is about -2.3V. But we all know well that the MOSFET specs around the gate threshold voltages are all over the place (e.g. the data sheet claims -1.5V > Vgs(off) > 3.5V)-, as well as the transconductance, etc. No precision here, you need to manually select the devices, but most of the cases this is not necessary. The DN2540 is better suited for higher currents where is more linear and also transconductance is higher (see below).

Tracing the characteristic curves for low voltages is somehow challenging. I found a small hump in the saturation region which created a minor negative resistance on Rds when looking at >30V. I’m not sure whether this was due to the tracer or my tracing setting. I have to confess that I’m not that experienced with Locky’s ICT.

The DN2540 needs to operate at VDS>1-1.3V to run out of the triode region. The increase of transconductance at higher current can be seen with more space between the curves. Also rds decreases significantly at higher currents. This is difficult to see on the below curves:

I checked this with the Spice model provided by Supertex and was surprised to see that Rds reduced from 17kΩ (Id=10mA) down to 10kΩ (Id=40mA) and  3.5kΩ (Id=50mA) even 700Ω at high currents (e.g. Id>50mA). The transconductance on the other hand increases x2.3 from 120mA/V to 280mA/V (Id=40mA) or 300mA/V (Id=50mA) or x2.5.  The net effect is that the mu drops massively at this operating point which makes the DN2540 not that great in my opinion for higher currents.

This made me think on the following quote from Morgan’s book:

“The device has a maximum continuous current of 500mA, so it should come as no surprise to learn that performance degrades at low currents. If you need a current <10mA, then you owe it to yourself to see if there’s an alternative solution because the device is much better >10mA, and at 25mA it really comes alive (rout of a cascode CCS at 25mA was four times that at 10mA, all other factors kept constant).”  – from Morgan Jones’ “Valve Amplifiers 4th Edition”

Surely the above makes sense from a transconductance perspective, but Gm is only x2 which would yield the x4 improvement mentioned by Morgan Jones, however this assumes that rds remains the same or in other words, the gain (μ) also duplicates.

What good doesn’t look like

My observation from tracing the DN2540 and Morgan’s statements pushed me to explore this a bit further. I proceeded to test this rationale by firstly producing the FET curves at low VDS with LTSpice and looking at rds. I was surprised to see x1.85 reduction in rds down from 13kΩ to 7kΩ from 10mA to 50mA. This should be reflected surely in the CCS then assuming the LTSpice model created by Supertex is accurately. What gave me a bit of confidence was that my findings on rds correlated with the model despite the challenges I faced to determine rds when tracing this FET.

The CCS performance degraded from 380MΩ down to 70MΩ between 10mA and 50mA in the simulations. Ok, wait a minute. The programming resistor Rs is reduced 6.5 times from 130Ω  to 20Ω. Gm is increased 2.5 times (from 120 to 300mA/V – from my traces).

Considering these differences in Rs, Gm and rds we should expect at least 3.56 times reduction on Rout. This is not far off from the results in the simulations.

So I’d be interested to see how Morgan Jones got to the conclusion of x4 performance improvement 🙂

As we mentioned before, the poor frequency response of this CCS is due to the output capacitance (Coss) mainly. Plotting the impedance versus frequency we can see that above 100Hz the CCS impedance falls dramatically. This is not the end of the world as the CCS can be very effective to provide a sterling PSR at 100Hz. I used the CCS + VR combination in the past and I have to report again (and again) that delivered a hum free supply in my preamplifiers or amps.

Walt Jung came up with a great idea “bias multiplier” as he called it to address the Coss problem. This is shown in the below diagram and simulation:

We can see that the frequency response is improved at HF thanks to driving the bottom FET (M3 in the above circuit) to a higher VDS level. A bigger R5 and R6 divider is needed to push M3 VDS above 20V but this may be a challenge in real life due to size of the resistors. The added penalty is that the impedance is reduced slightly due to the shunt path provided by R5 and R6.

This  is to be continued…