Finally after many years, I managed to document this great PCB. If you already have this PCB and want the build guide and BOM please let me know.
Here is an extract of the build guide for the ones who are interested in this circuit:
Introduction
The capacitor multiplier circuit often gets overlooked in the valve circuit designs. It’s a fantastic circuit to achieve an extremely quiet power supply. It’s not a regulator as such, as it’s doesn’t have a feedback loop/mechanism to regulate the output voltage and therefore it doesn’t affect the sound of the amp in the same way a regulated power supply does. Therefore, it’s an attractive circuit to be used in hi-fi designs in my opinion as many get put off by the “sound” of regulators. In particular, when you are looking for a very quiet power supply (e.g. phono stage or preamp).
With a capacitor multiplier circuit, you can achieve high level of PSR (Power Supply Rejection) compared to passive filtering networks. Easily rejection of over 50dB can be achieved and you should expect it to be in order of 80 to 100dB. In practice you will get noise coupled/induced to the circuit through cable layout, etc so at least 50dB is easily achievable, which is a fantastic result.
However, there is no free lunch am afraid. There is a price we pay on this circuit, and it’s not the cost of the components. MOSFETS and even good quality film capacitors (e.g. WIMA DC-Link) are relatively inexpensive in the grand scheme of things. The big issue that we may end up with is the heat dissipation depending on the load we are planning to use this circuit. You may end up wasting too much heat and requiring a big heatsink for the pass MOSFET, hence this circuit isn’t practical for an amplifier. I don’t recommend using it for an amp, you have been warned!
The circuit
I assume you have a good electronic engineering background and you know what you are doing here. If you’re not able to design your capacitor multiplier circuit, I’d recommend you replicate an existing one or not use this circuit at all.
Having said that, it’s a very simple circuit and easy to use. If you want to learn about this topic, do a bit of a research on classic text books as it is well covered or the following one: “Designing Power Supplies for Valve Amplifiers”, “Designing a MOSFET capacitor multiplier”, page 138, Merlin Blencowe, 2010.
The basic capacitor multiplier circuit is shown on the figure below. The output voltage is set by the VREF voltage minus the VGS (sat) of the PASS MOSFET. To dial this voltage, you need a resistor divider which is formed by several resistors on my PCB. R6 and R7 are split to allow you using different resistor and not bother about the voltage rating too much. The total resistor divider is formed by R5+P2 as upper part and R6+R7 as the lower part. The combination of R5 and P2 gives you fine tuning as well as ensuring the power rating of the trimmer resistor. The charging time of C2 will dictate the gentle ramp up of the voltage. You can do the maths or an LTSpice simulation will help you if you are a bit lazy.
You may be asking what is the role of C1 and can you omit it? The answer is no, you cannot. C1 is key to provide a low impedance to the drain of the MOSFET. The drain is high impedance and you certainly don’t want a high-impedance node at the input as higher ripple and/or oscillation may occur. It will also provide additional filtering. Anywhere between 10 and 47uF will work fine.
C3 is not that critical but I find it to be useful to have a film capacitor there as they sound much better than electrolytics in my experience, the WIMA DC-LINK in particular. The PCB has flexibility to accommodate multiple version and sizes, so have a look at the BOM to see what works best for you.
The higher the overall resistance across R5+P2 and R6+R7 the better. You will get a slower turn-on constant which is beneficial to your valves during the warm up period as well as lower dissipation requirements on the resistors due to lower current consumed.
Let’s talk about the protection diodes in this board. D2 allows a discharge path for C3 (and beyond) when the MAINS power is disconnected. This will protect M5 for a reverse voltage.
Second protection is provided by D3 and D4 zeners. These are required unless the device used in M5 has protection diodes embedded. Otherwise, you may damage the gate by exceeding the maximum VGS allowed. Clamping it to 15V is safe enough. C2 gets to discharge through the resistor divider when the power is off.
Now, if you want to go a step further in power supply noise rejection, you can implement the below circuit which is the ultimate cap multiplier contraption:
The above diagram shows the addition of the CCS in replacement for the upper leg of the resistor divider network. In this way, we provide further noise rejection and a small constant charging current to C2. To ensure you deliver a voltage below IN level and desired to your application, there is R4 and P1 to set the output voltage like in the resistor divider circuit explained earlier. In this case they will set a reference voltage from the constant current set by the CCS. It’s important that you keep 25V at least across the CCS and 30V between output and input to operate properly. The addition of the CCS will increase the power dissipation requirements of the MOSFET due to this constraint.
The way the CCS is implemented on the board is shown below:
The cascoded pair of FETs formed by M1/M2 and M3/M4 will provide you the CCS required. You can either use the simple pair of LND150s or replace the top LND150 for a beefer MOSFET if you are operating closer to 500V at the input. In that case you can install an IXTP08N100D for example in TO-220 case instead of M2. If you want much better stable temperature, you can also implement a J112 jFET on M4 instead of the LND150 on M3 and set it to about 1mA of operation with a 2K2 resistor in R3. If you use a jFET then you will need to install D1 15V Zener. You can play with different jFETs you may have around to create the reference current. Make sure you set R3 correctly for the right current and jFET TEMPCO. There is an outstanding reference book to look into if you want to get further in-depth view of the CCSs: “Current Sources and Voltage References” from Linden T. Harrison, Newnes Elsevier, 2005.
You want to protect the MOSFET from a short circuit scenario or for overcurrent in some cases. There is a big resistor R10 to be installed in the board for some basic current limiter in series with For a more advanced current limiter circuit, you can implement the addition of the T1 transistor. The T1 transistor will cutoff the MOSFET once the voltage across R10 reaches the saturation voltage of the transistor. This makes it simple to dial to a degree the current threshold for the limiter circuit. Simply divide 670mV by the maximum current before the limiter kicks in. Be sure that this limit is beyond the maximum peak current required by your load. I’d give good headroom here to avoid the cap multiplier imprinting some sonic signature in your preamp/stage. For example if normal operation is 20mA, I’d set the protection to 200mA to ensure that it only operates in an abnormal situation.
Optionally, you have a NEON bulb to install in case you want some indication of the output voltage and cap multiplier operation. Useful to have, but if the board is inside a case, you will need to solder wires to extend the connection to the NEON bulb. R11 needs to be sized according to the NEON bulb used and the output voltage of the cap multiplier.
Below is a simple workbench test example for my phono circuit. A noisy raw power supply was used during test and a 20mA load used. You can see the 50Hz peak reduced over 50dB. Likewise, all upper harmonics over 100Hz get squashed down to -100dB floor, quite impressive for a simple circuit. This test shows how 300mV ripple is reduce to less than 1mV. In fact, the circuit was tested on a bench and without any case/shielding so there is Mains noise creeping everywhere on the leads.
With a passive cap multiplier (i.e. without a CCS) you should ensure at least 10V between input and output. That will ensure the correct operation of the PASS MOSFET whilst keeping as low as possible the dissipation on the MOSFET. Similarly, when a CCS-type circuit is used, you should allow 30V between input and output. The higher the input voltage, the more you will push the PASS MOSFET to dissipate. Sometimes is even easier to have a high-power dropping resistor (e.g. clad wirewound type) to dissipate and lose a few volts before the input of the cap multiplier. It’s easier to dissipate Watts on the clad resistor compared to a MOSFET which will need a bigger heatsink instead.
Circuit example: Phono stage
Below is an implementation I used for a phono stage. I used both electrolytic caps for C1 and C2, whereas the final capacitor C3 is film. R10 is set to provide 200mA current limit. Output voltage is dialed by P1 which is 500K trimpot.
Today, I would use a better MOSFET like the STF3LN80K5. This is a plastic package TO-220FP which is more convenient as it’s isolated.
Ale: I built one of your Cap Multipliers for my tube (6H30) head amplifier. Quiet as a graveyard at midnight! Very pleased with it. gd
Great to hear Geoff! I should have added the HP amp as use case, which is very appropriate. Thanks for the feedback
Hi Ale,
Have you considered another another variable ie substituting a stack of zeners for R4 & P1/R6 & R7 to give a voltage “stabiliser”? Better still, how about a wee daughter board so a LR8 can be used to set the stabilised voltage—along with a built in low pass filter. There are perhaps “better” voltage regulators but the above would increase the usability (and hopefully sales) of your PCB.
tim
Hi Tim,
Yes I have. In fact I have different regulators on PCB to be used. I was thinking on building something small with the LR8 but not sure if it’s worth the effort. I’ve used it before though successfully for screen voltage regulation.
This PCB is intended for a cap multiplier filtering without regulation. The combination of CCS with resistor to create voltage reference is far superior to a zener string should anyone is looking for a stabilised voltage without regulation. In fact, adding a regulator after a cap multiplier allows you to have a higher pole on the feedback loop which reduces the interaction in the audio band which will make it desirable. I haven’t implemented that yet and should be a good experiment to do.
Otherwise, cap multiplier only is a great choice in audio circuits! Have you ever added a voltage regulator to an output stage? I did to my 45 SE for fun. It sounded dead quiet but super dull!
Cheers, Ale
Hi Ale,
I’m glad to see the new article.
I just rewired the Gyrator not long ago, modifying it into this design (to use the LND150 CCS).
May I ask if there is a significant difference in the types of pass MOSFETs used? (I originally continued to use the IXTP3N100D2).
Ivan
Hi Ivan,
Sure, you can reuse the gyrator PCB to work as a cap multiplier or voltage reference. That FET is ok, you want lower capacitances to keep noise out. There are other FETs with much lower input capacitance, but you should be fine in most of the cases as the LND150 CCS is already attenuating a lot the input noise.
Ale, What size is the CM pcb? My apologies if I’ve missed that bit of info. best t
It’s 60mmx132mm. A big board due to film cap sizes.
Cheers, Ale
I did something very similar for the HV PSU of my OSDEHA headphone amplifier. Works very well — except that there’s an issue with the current limiter to protect the circuit from accidents like shorts on the output. If the output is shorted, the Emitter of the T1 will be at 0V, while the collector sees the high voltage stored in C2. As far as I can tell, most BJTs will consider to blow up just from this. Also, once the Base-Emitter voltage exceeds 0.6 V, the BJT will turn on, shorting C2 to GND. If T1 is not dead yet, the current flow from C2 through T1 to GND will put an end to T1.
This is not just theory, but hard reality. While testing the OSDEHA, I had a number of hickups, and everytime the BJTs and the FETs went kaputt. I’d be happy to learn if anyone has a better idea for a simple output protection that can be used in a cap multiplier like this.
Well, with the right BJT with VCEO and VCBO which are over the voltage levels used it should work ok providing the cap is small. Otherwise if you’re expecting regular shorts and want full protection you may need a series resistance with the output of the cap to limit the transient current.
Let’s say the cap is charged to 400 V. I don’t see how a typical BJT would survive that voltage.
A current limiting resistor would help, but it would (i) either sit between the cap and the gate of the FET, or (ii) between the BJT and the FET gate.
In the first case, the resistor would decouple the FET from the cap, which would reduce the performance of the cap multiplier.
In the second case, the voltage drop across the resistor would decouple the FET gate from the BJT, preventing the BJT from protecting the FET.
(Yes, I tried both of these options, no joy.)
(i) if the series resistor is small it won’t interact with Cgs and hence won’t impact HF performance
(ii) if the series resistor is small and at the collector position, the voltage drop won’t be large enough (e.g. Vgsth = 4V) to prevent turning off the FET.
I think if you design it properly it would work.
Ok, so the trick would be to find a BJT part that can survive at high voltages and currents, and use a small enough resistor that would not interfere with the performance of the cap multiplier or the current limiter. I don’t see how this compromise can be realised, but maybe you can suggest some BJT parts and resistor values that would work?
It’s a piece of work of formulae work or Spice simulation, can you do that? I’ve got not the time now to do it, but shouldn’t be too much work. You should also look at the SOA graphs of the BJT. You can look at the SOA graph of the ZTX458 for example and find out the peak discharge currents that can withstand before frying up. ZTX458 datasheet.
From about 2mA (DC) to 200mA in 100uS. It’s an RC calculation exercise, but Spice would be good tool to leverage here. I’d be inclined that the series resistor before the gate and collector node is the best choice.
I am clueless with SPICE, but… looking at the datasheet, the ZTX458 could withstand 20 mA for T = 100 ms at 400 Vce. With a 4.7 uF cap (C2 in your schematic), and T = R x C2, so we get R = 21 kOhm. This means one would need to insert a 21 kOhm or larger resistor (i) either between C2 and the FET gate or (ii) at the C or E pins of the BJT to keep the BJT alive. I don’t think such a high resistance value is a good idea, because it would (i) either decouple the FET gate from the voltage reference or (ii) slow down the current limiter too much, making it ineffective (0.1 seconds can be pretty long for a shorted FET).
Also my 400 V example was just an example. Going to higher voltages it becomes difficult to find a small BJT that will take more than 400 V.
I really feel there should be a better solution for the protection circuit.
P.S.: I clicked “notify me of follow-up comments by email”, but never received a message. What’s up with this?
I do get the notifications, worth checking the SPAM filter you may have with google mail?
I don’t think you are looking into transient analysis here, static DC response and calculations won’t work. That is why I suggested SPICE to look at the time response and adjust as needed.
(i) can you please expand technically how much decouple you think there is? Ciss of the FET in follower mode is pretty low.
(ii) how do you think the slow down occurs when the FET is turned off providing the sense current is given the BJT the voltage drop needed (including the additional resistor) to operate. You haven’t drawn down any equation, nor simulations so am scratching my head to see how you can easily got to that conclusion.
If you want protection at higher voltage, consider something like STX616 or another BJT with VCE of 1KV, etc.
As I said, I have no clue about SPICE, so all I can do is to try understand what’s happening in the circuit without the help of a simulator.
(i) Inserting a 21k resistor between C2 and the FET gate just seems wrong to me. I’d say you want the gate directly at the cap to get the most out of the cap multiplier. One may have to use a gate stopper (330 Ohm in your schematic), but this is usually chosen as low as possible. A (much) larger resistor will degrade the performance of the cap multiplier at high frequencies.
(ii) C2 and the additional resistor form an RC circuit with a time constant of 100 ms. In other words, it takes a lot longer than 100 ms to fully discharge C2. The FET gate will remain high during this time, and the FET will not shut down quickly enough to protect it from the overcurrent.
Any thoughts on what to do for volages higher than 400 V?
(i) “just seems wrong to me” has no technical justification. Calculate the 3dB pole at the frequency given your FET’s Ciss and then you can revisit your statement
(ii) I think you’re missing the point that it’s feedback system and the BJT is protecting the FET by not exceeding the current which will always be below the threshold defined. So I don’t get why you worry of “taking longer” to discharge providing the FET is safe as well as the rest of the circuit. Again, no technical justification provided.
(i) With a 21k resistor and an assumed 1 nF gate capacitance, the time constant is 21 microseconds (or 7.5 kHz). If a FET with a very low capacitance is used, this can probably reduced to single-digit microseconds (50 kHz or so), which is much better, but still not great.
(ii) Even though the BJT is fully turned on, the voltage drop across the 21k resistor at the BJT will prevent the gate from being fully pulled down to the voltage needed to attain the desired current limit. The current through the FET will therefore be too high, and things may blow up.
You are using poor values for Ciss and incorrect assumptions
Without the resistor you get a theoretical -104dB PSRR over 10kHz, worse at LF unless you add a CCS to the vREF. If you add a 10K resistor at Vref, the current peak will be only 10mA and keep the BJT below 200mW (peak) for a short of 20S (example) in a circuit providing 280V output and with a 3R threshold resistor. The pass MOSFET (a decent one not the poor one you have chosen in your example) will only deliver 300mA peak before flatting to 200mA during the short period. A fuse or the drain resistor should hit first before the MOSFET SOA is surpassed.
Frequency-wise, the penalty on rejection is 40dB and rejection is still below -64dB up until 10kHz and goes down from there to over -100dB. Still more than good.
Now if you don’t know how to design these circuits, stay away but don’t make lose statements without the proper technical analysis and backed up with real data, simulations or formulae.
You will need to add protection at the drain, like a 470R resistor with enough power to sustain the short or use it as a fuse (much better).
Quite tired of this discussion and don’t want to waste more of my time, I’ll keep the simulation data to myself and may share it another time.
Hi! Maybe this is a philosophical (or semantic) question, but isn’t the version with the CCS a regulator without feedback loop? The CCS forms a voltage reference with R4/P1 and at least in LT Spice Vout doesn’t follow Vin, while the version with the resistive divider follows Vin.
Anyways, I’m currently building the CCS version for a 211 output stage and am curious if and how it touches dynamics. I also had the experience that regulators in output stages make the amp sound dull. Changing to an LC with a Q 0.7 per channel worked objectively way better.
Best,
Daniel
Hi Daniel, you’re right and worth pointing it out. In fact, either option take the reference from the voltage input and not the output so the feedback loop (if we can call it that way) is from the input which has the pass MOSFET in between which massively reduces its output feedback. As you well say, with the CCS that is even more dramatically reduced than the resistor divider. For practical purposes in my opinion, I consider negligible the contribution from the output so there is no “feedback”.
The CCS-based option has several advantages as pointed out before but it comes at a cost of extra components.
Good luck with your build!
Ale
Thanks! I ran into a few issues and I’ll post a few notes for anybody else building HV cap multipliers:
I have an CLCLC supply before the multiplier. Inductor kickback gave a huge voltage spike when the pass FET turns on. Freewheeling diodes fixed that.
I first ignored the mention to “replace the top LND150 for a beefer MOSFET if you are operating closer to 500V at the input.” thinking it’s elevated through R4/P1 anyways. Use a top FET that can handle the full input voltage.
The MSC750SMA170B works well as a pass FET for higher voltages.
Best,
Daniel
Hi Daniel,
Thanks for sharing your useful experience. The CCS gets exposed to full voltage during start up and charging cycle of C2. I considered adding a zener at the input but I thought that voltage protection should be considered on the raw side, otherwise a zener could cause some damage earlier on.
The MSC750SMA170B seems like a nice SiC FET, haven’t tried it though. Cheers, Ale