Playing with various SE designs recently I got into refining a bit the fixed bias circuit. The above version, which is still under revision, is a good improvement to what I used before in my 45SE. The raw supply doesn’t need a large filtering stage. In fact, the capacitor multiplier (formed by Q1, R1 and C1) provides about 62dB noise rejection at 100Hz. This is about x1000 reduction factor!. If you consider that bias current is less than 2mA, you can arrive at your own conclusions regarding the filtering required. The bias voltage is set by the divider formed by R2, R3 and the potentiometer. I like using the 5T/10T ones. In this design, about 6V of bias span is provided. D2 provides a way to avoid C2 to discharge in case of an interruption of power and expose the output valves to current surges (and potential damage). C2 helps stabilising the FET voltage. With the BS170 biased at 1mA approx gives an output impedance of 50Ω. If higher transconductance FETs are used, then impedance can be lowered down to 5-8Ω (e.g. if using the IRF610) but you need to pump up the bias current.